The invention herein described was made in the course of or under a contract or subcontract thereunder, (or grant) with the Department of the Air Force.
This invention relates to a circuit for a digital data receiver for use in recovering a clock signal which may be of variable rate. Prior art U.S. patents of interest include U.S. Pat. No. 3,238,462 to Ballard et al, U.S. Pat. No. 3,142,802 to Maure, U.S. Pat. No. 3,731,220 to Besenfelder and U.S. Pat. No. 3,798,573 to Seidel.
Most digital transmission systems operate at a single clock rate or at a limited number of standard clock rates due to the difficulty of recovering from the received signal a clock signal that varies over a wide band of frequencies. In such limited clock-rate digital communications systems, clock recovery in the receiver is accomplished with the use of tracking filters, pilot tones, etc. In fixed-rate clock recovery systems, the demodulated data is reshaped to obtain a spectral line at the clock rate. The reshaped signal is band-pass filtered to improve the signal-to-noise ratio and conducted through a tracking filter or phase-lock loop to further enhance the signal-to-noise ratio.
In a digital data receiver intended to receive binary data having an associated clock rate that may vary over a wide band of frequencies, with end points of the band forming a ratio of 8 to 1 or greater, the use of the conventional clock recovery technique described in the preceding paragraph would entail the use of a multitude of filters and electronically controlled oscillators, an impractical requirement.